Semiconductor device

ABSTRACT

A semiconductor device includes a semiconductor layer of a first conductivity type having first and second surfaces and an impurity concentration distribution in a first direction from the second surface to the first surface, a first semiconductor region of a second conductivity between the semiconductor layer and the first surface, a second semiconductor region of a first conductivity type between the first semiconductor region and the first surface side, a first trench extending from the first surface into the semiconductor layer, a first electrode located in the first trench over a first insulating film and spaced from the first semiconductor region by a first insulating film, a second electrode located in the first trench over a second insulating film, a second trench extending from the first surface into the semiconductor layer and surrounding the first trench, and a third electrode located in the second trench over a third insulating film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2018-027575, filed Feb. 20, 2018, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A power semiconductor device is required to have both high breakdownvoltage and low on-resistance, but in general, there is a trade-offrelationship between a breakdown voltage and on-resistance of thedevice.

Among power field effect transistors (power MOS transistor) having atrench gate, a power MOS transistor having a field plate electrodeburied in a trench and having a distribution of an impurityconcentration in a direction from the bottom portion side to the upperside of the trench in a drift region where electrons travel is known.

By combining the trench type field plate electrode and the impurityconcentration distribution of the drift region, the electric fielddistribution of the drift region is more uniform, and the trade-offbetween the breakdown voltage and on-resistance of an active region isimproved.

However, when the impurity concentration distribution described aboveand the termination structure of the related art are combined, since theimpurity concentration is constant in the longitudinal direction of thetrench in the termination region, there is a problem that the sameelectric field distribution as the active region may not be obtained andthe breakdown voltage of the termination region is decreased.

DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams showing a semiconductor device according toEmbodiment 1.

FIGS. 2A to 2C are diagrams showing an impurity concentrationdistribution of the semiconductor device and an electric fielddistribution of an active region according to Embodiment 1.

FIGS. 3A to 3C are diagrams showing an electric field distribution of atermination region of the semiconductor device according to Embodiment1.

FIGS. 4A to 4C are diagrams showing an electric field distribution of atermination region of a semiconductor device of a comparative exampleaccording to Embodiment 1.

FIGS. 5A to 5C are cross-sectional views sequentially showing amanufacturing process of the semiconductor device according toEmbodiment 1.

FIGS. 6A to 6C are cross-sectional views sequentially showing amanufacturing process of the semiconductor device according toEmbodiment 1.

FIGS. 7A to 7C are diagrams showing an impurity concentrationdistribution of the semiconductor device and an electric fielddistribution of an active region according to Embodiment 2.

FIG. 8 is a diagram showing another impurity concentration distributionof the semiconductor device according to Embodiment 2.

FIGS. 9A to 9C are diagrams showing an impurity concentrationdistribution of the semiconductor device and an electric fielddistribution of an active region according to Embodiment 3.

FIGS. 10A to 10C are diagrams showing an electric field distribution ofa termination region of the semiconductor device according to Embodiment3.

FIG. 11 is a diagram showing another impurity concentration distributionof the semiconductor device according to Embodiment 3.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device capable of improving abreakdown voltage of a termination region.

In general, according to one embodiment, a semiconductor device includesa semiconductor layer of a first conductivity type that includes a firstsurface and a second surface opposite to the first surface and has animpurity concentration distribution in a direction from the secondsurface side to the first surface side, a first semiconductor region ofa second conductivity type that is provided at a midpoint between thesemiconductor layer and the first surface side, a second semiconductorregion of a first conductivity type provided in a midpoint between thefirst semiconductor region and the first surface side, a first trenchthat is provided at a midpoint between the semiconductor layer and thefirst surface side, a first electrode that is provided in the firsttrench via a first insulating film so as to face the first semiconductorregion, a second electrode that is provided in the first trench via asecond insulating film, a second trench that is provided at a midpointbetween the semiconductor layer and the first surface side so as tosurround the first trench, and a third electrode that is provided in thesecond trench via a third insulating film.

Hereinafter, embodiments of the present disclosure will be describedwith reference to drawings. In the following description, the same orsimilar members and the like are denoted by the same reference numerals,and the description of the members and the like once described isomitted as appropriate.

In addition, in the following description, the relative impurityconcentrations of the respective conductivity types may be representedby n⁺, n, n⁻, n⁻⁻, and p⁺, p, p⁻, p⁻⁻. That is, n⁺ indicates that ann-type impurity concentration is relatively higher than that of n, n⁻indicates that the n-type impurity concentration is relatively lowerthan that of n, and n⁻⁻ indicates that the n-type impurity concentrationis relatively lower than that of n⁻. In addition, p⁺ indicates that ap-type impurity concentration is relatively higher than that of p, p⁻indicates that the p-type impurity concentration is relatively lowerthan that of p, and p⁻⁻ indicates that the p-type impurity concentrationis relatively lower than that of p⁻. In some cases, n⁺ type, n⁻ type,and n⁻⁻ type are simply described as n type, and p⁺ type, p⁻ type, andp⁻⁻ type are simply described as p type.

In the present specification, the p-type impurity concentration means anet p-type impurity concentration. The net p-type impurity concentrationis the concentration obtained by subtracting an actual n-type impurityconcentration from an actual p-type impurity concentration of thesemiconductor region. Similarly, in the present specification, then-type impurity concentration means a net n-type impurity concentration.The net n-type impurity concentration is the concentration obtained bysubtracting an actual p-type impurity concentration from an actualn-type impurity concentration of the semiconductor region.

Embodiment 1

In general, according to one embodiment, a semiconductor device includes

a semiconductor layer of a first conductivity type having a firstsurface and a second surface opposite to the first surface and animpurity concentration distribution in a first direction from the secondsurface to the first surface, a first semiconductor region of a secondconductivity located between the semiconductor layer and the firstsurface, a second semiconductor region of a first conductivity typelocated between the first semiconductor region and the first surfaceside, a first trench extending from the first surface into thesemiconductor layer, a first electrode located in the first trench overa first insulating film and spaced from the first semiconductor regionby a first insulating film, a second electrode located in the firsttrench over a second insulating film, a second trench extending from thefirst surface into the semiconductor layer and surrounding the firsttrench, and a third electrode located in the second trench over a thirdinsulating film.

FIGS. 1A and 1B are diagrams showing a semiconductor device according tothe present embodiment, FIG. 1A is a plan view thereof, and FIG. 1B is across-sectional view taken along the line A-A of FIG. 1A and viewed inthe direction of the arrow.

FIGS. 2A to 2C show an impurity concentration distribution of thesemiconductor device and an electric field distribution of an activeregion, FIG. 2A is the same as FIG. 1B, FIG. 2B is an impurityconcentration distribution diagram, and FIG. 2C is an electric fielddistribution diagram.

FIGS. 3A to 3C are diagrams showing an electric field distribution of atermination region of the semiconductor device, FIG. 3A is an enlargedplan view near the boundary between the active region and thetermination region, FIG. 3B is a cross-sectional view taken along lineB-B of FIG. 3A and viewed in the direction of the arrow, and FIG. 3C isan electric field distribution diagram.

First, the outline of the semiconductor device will be described.

As shown in FIGS. 1A and 1B, a semiconductor device 10 of the presentembodiment is a vertical power MOS transistor having a trench gate and afield plate electrode buried in the trench.

The semiconductor device 10 includes an active region 10 a and atermination region 10 b surrounding the active region 10 a. The activeregion 10 a functions as a region through which a current flows when thesemiconductor device 10 is turned on. The termination region 10 bfunctions as a region for balancing the electric field applied to theend portion of the active region 10 a when the semiconductor device 10is turned off and improving the breakdown voltage of the semiconductordevice 10.

In the active region 10 a, a plurality of first trenches 14 extending ina first direction (X direction) are provided at a predetermined intervald1 from one another in a second direction (Y direction) orthogonal tothe first direction. Each first trench 14 has, for example, a stripeshape. In the termination region 10 b, a second trench 19 is disposed soas to surround the plurality of first trenches 14. The second trench 19has, for example, a frame shape. The distance (interval dx in the Xdirection and interval dy in the Y direction) between each first trench14 and the adjacent portion of the second trenches 19 is substantiallythe same, and is a predetermined interval (d1=dx=dy).

The opposed end portions of each of the first trenches 14 extend beyondthe active region 10 a and into the adjacent portions of the terminationregion 10 b. FIG. 1A shows a case where six first trenches 14 extend inthe active region 10 a, but there is no particular limitation on thenumber of the first trenches 14 extending in the active region 10 a.

The semiconductor device 10 is provided with an n-type (firstconductivity type) semiconductor layer 11 that includes a first surface11 a and a second surface 11 b located opposite to the first surface 11a, and has an impurity concentration distribution in a direction fromthe second surface 11 b side toward the first surface 11 a side thereof(Z direction).

The semiconductor layer 11 is provided on a semiconductor substrate 22,and the second surface 11 b is in contact with the semiconductorsubstrate 22. A drain electrode (not shown) is provided on thesemiconductor substrate 22. The semiconductor substrate 22 is, forexample, a silicon substrate.

A p-type (second conductivity type) p base region (first semiconductorregion) 12 is provided between the semiconductor layer 11 and the firstsurface 11 a. An n⁺ source region (second semiconductor region) 13 isprovided between the p base region 12 and the first surface 11 a.

The first trench 14 extends from the first surface 11 a inwardly of thesemiconductor layer 11. A gate electrode (first electrode) 16 isprovided in the first trench 14, over a gate insulating film (firstinsulating film) 15, and faces the p base region 12.

Further, a first field plate electrode (second electrode) 18 is providedin the first trench 14 over a first field plate insulating film (secondinsulating film) 17.

Here, the gate electrode 16 is surrounded by the first field plateinsulating film 17 and the gate insulating film 15 and is physicallyseparated from the first field plate electrode 18.

The second trench 19 extends from the first surface 11 a inwardly of thesemiconductor layer 11 and surrounds the first trench 14. A second fieldplate electrode (third electrode) 21 is provided in the second trench 19over a second field plate insulating film (third insulating film) 20.

An interlayer insulating film 23 is provided on the p base region 12 andthe first field plate insulating film 17. A source electrode 24 isprovided on the interlayer insulating film 23. The source electrode 24is connected to the side surface of an n⁺ source region 13 and the pbase region 12 through an opening provided in the interlayer insulatingfilm 23. The first field plate electrode 18 may be connected to thesource electrode 24.

There may be a case where the p base region 12 is not provided betweenthe second trench 19 and the adjacent first trench 14.

Next, the breakdown voltage in the active region of the semiconductordevice will be described.

As shown in FIG. 2B, in the direction (Z direction) from the secondsurface 11 b side to the first surface 11 a side, the semiconductorlayer 11 includes a first portion 11 c having a first impurityconcentration n1, a second portion 11 d having a second impurityconcentration n2 higher than the first impurity concentration n1, and athird portion 11 e having a third impurity concentration n3 equal to thefirst impurity concentration n1. That is, the semiconductor layer 11 hasthree levels of impurity concentration distribution represented byn1=n3<n2.

The second portion 11 d is provided closer to the second surface 11 bside of the semiconductor layer 11 than the gate electrode 16 and closerto the first surface 11 a side of the semiconductor layer 11 than thebottom portion of the first trench 14 closest to the semiconductorsubstrate 22. The third portion 11 e is provided closer to the secondsurface 11 b side of the semiconductor layer 11 than the gate electrode16 and closer to the first surface 11 a side of the semiconductor layer11 than the second portion 11 d. The thicknesses of the first portion 11c, the second portion 11 d, and the third portion in the third directionmay be essentially the same.

The broken line shown in FIG. 2B shows the impurity concentrationdistribution of the semiconductor device of a comparative example. Inthe semiconductor device of the comparative example, the impurityconcentration distribution is substantially constant.

As shown in FIG. 2C, both the electric field distribution (solid line)of the active region 10 a and the electric field distribution (dashedline) of the active region of the comparative example in the presentembodiment have electric field peaks at two locations, at the lower endof the gate electrode 16 and at the bottom of the first trench 14 and alower electric field between the two points, that is, the electric fieldhas a so-called bimodal distribution. Since the breakdown voltage valuecorresponds to the lowest electric field value, in order to improve thebreakdown voltage, it is necessary to increase the value of the electricfield between the peak values of the bimodal distribution to make theelectric field distribution more uniform.

In the semiconductor layer 11 of the present embodiment, the n-typeimpurity concentration in the second portion 11 d is higher than that inthe comparative example. As a result, the drain voltage increases and apunch-through state occurs when a depletion layer reaches the secondportion 11 d of the semiconductor layer 11 having a high impurityconcentration, whereby the electric field is increased as compared withthe semiconductor layer of the comparative example. As a result, thebreakdown voltage in the active region 10 a is improved and theon-resistance of the device is reduced.

The breakdown voltage in the termination region of the semiconductordevice will be described.

As shown in FIGS. 3(a) and 3(b), in the termination region 10 b of thepresent embodiment, the frame-shaped second trench 19 is disposed so asto surround the stripe-shaped first trench 14. In the second trench 19,the second field plate electrode 21 is buried over the second fieldplate insulating film 20. The second field plate electrode 21 may beconnected to the source electrode 24 as is the first field plateelectrode 18.

Each of the first trench 14 and the second trench 19, the first fieldplate insulating film 17 and the second field plate insulating film 20,and the first field plate electrode 18 and the second field plateelectrode 21 have substantially the same structure. Substantially thesame includes not only the structure being completely identical but alsothe structure is sufficiently similar to the extent that the intendedeffect of action is obtained.

Specifically, the first trench 14 and the second trench 19 have the sametrench width and trench depth. The first field plate insulating film 17and the second field plate insulating film 20 have the same filmcomposition and thickness. The first field plate electrode 18 and thesecond field plate electrode 21 have the same film composition.

As a result, the portion of the first trench 14 and the second trench 19in the termination region 10 b have the same structure as the adjacentportion of the first trenches 14 in the active region 10 a.

Therefore, as shown in FIG. 3C, since the electric field distribution ofthe termination region 10 b is substantially the same as the electricfield distribution of the active region 10 a, it is possible to improvethe breakdown voltage of the termination region 10 b and have it beequal to the breakdown voltage of the active region 10 a.

FIGS. 4A to 4C are diagrams showing an electric field distribution of atermination region of the semiconductor device of the comparativeexample, FIG. 4A is an enlarged plan view near the boundary between theactive region and the termination region, FIG. 4B is a cross-sectionalview taken along line C-C of FIG. 4A and viewed in the direction of thearrow, and FIG. 4C is an electric field distribution diagram. Thesemiconductor device of the comparative example is a semiconductordevice in which the second trench disposed in the termination regiondoes not surround the first trenches.

As shown in FIGS. 4A and 4B, in a semiconductor device 40 of thecomparative example, a second trench 41 is disposed in parallel with thefirst trench 14 in the termination region 40 b. The second trench 41 hasa stripe shape like the first trench 14. In the second trench 41, asecond field plate electrode 43 is buried over a second field plateinsulating film 42.

As shown in FIG. 4C, in the termination region 40 b of the semiconductordevice 40 of the comparative example, the electric field shows adistribution having a peak in the third portion 11 e having a lowimpurity concentration, that is, a so-called unimodal distribution.Therefore, the electric field distribution is remarkably nonuniform ascompared with the bimodal distribution shown by the broken line in FIG.3C. In the termination region 40 b, since the impurity concentration isconstant in the longitudinal direction (X direction) of the first trench14, the breakdown voltage is lower than an active region 40 a.

Next, a method of manufacturing the semiconductor device 10 will bedescribed. FIGS. 5A to 6C are cross-sectional views sequentially showinga manufacturing process of the semiconductor device 10.

As shown in FIG. 5A, a semiconductor layer having a predetermined filmthickness and a predetermined impurity concentration is continuouslyepitaxially grown on the semiconductor substrate 22 by, for example, avapor growth method. Epitaxial growth is performed using, for example,hydrogen (H₂) as a carrier gas, dichlorosilane (SiCl₂H₂) as a processgas, and phosphine (PH₃) as a doping gas. In this manner, thesemiconductor layer 11 having the first portion 11 c having the firstimpurity concentration n1, the second portion 11 d having the secondimpurity concentration n2, and the third portion 11 e having the thirdimpurity concentration n3 is formed.

As shown in FIG. 5B, boron ions (B⁺) are implanted through the firstsurface 11 a and into a predetermined region of the semiconductor layer11 by ion implantation, for example. In this manner, the p base region12 is formed inwardly of the semiconductor layer 11 from the firstsurface 11 a.

Next, phosphorus ions (P⁺) are implanted through the first surface 11 ainto a predetermined region of the p base region 12. In this manner, then⁺ source region 13 is formed in the p base region 12 at and extendinginwardly of the semiconductor layer from the first surface 11 a.Activation annealing may be performed separately or simultaneously.

As shown in FIG. 5C, the first trench 14 and the second trench 19 aresimultaneously formed in the semiconductor layer 11 into the firstsurface 11 a by photolithography and Reactive Ion Etching (RIE), forexample. The first trenches 14 and the second trench 19 have the samewidth and the same depth.

As shown in FIG. 6A, an insulating film, for example, a silicon oxidefilm is formed on the inner surfaces of the first trench 14 and thesecond trench 19 by a Chemical Vapor Deposition (CVD) method, forexample, and a conductive film, for example, a polysilicon film isdeposited thereover. In this manner, at the same time that the firstfield plate electrodes 18 are formed in the first trench 14 over thefirst field plate insulating film 17, the second field plate electrode21 is formed in the second trench 19 over the second field plateinsulating film 20.

Next, as shown in FIG. 6B, the first field plate insulating film 17 inthe first trench 14 is recessed so as to expose the side surface of thep base region 12 by RIE, for example. An insulating film to be the gateinsulating film 15, for example a silicon oxide film, is formed on theinner wall of the exposed first trench 14 by a thermal oxidation method,for example, and a conductive film to be the gate electrode 16, forexample a polysilicon film, is formed by the CVD method.

Next, as shown in FIG. 6C, an insulating film to be the interlayerinsulating film 23 covering the entire surface of the first surface 11 aof the semiconductor layer 11, for example a silicon oxide film, isformed by CVD, for example. A contact hole 25 extending through the n⁺source region 13 to the p base region 12 is formed in the interlayerinsulating film 23 by RIE, for example.

A metal film to be the source electrode 24, for example an aluminum (Al)film, is formed on the interlayer insulating film 23 so as to fill thecontact hole 25 by, for example, sputtering. In this manner, thesemiconductor device 10 shown in FIGS. 1A and 1B is obtained.

As described above, in the semiconductor device 10 of the presentembodiment, the semiconductor layer 11 has three levels of impurityconcentration distribution represented by n1=n3<n2 and the secondtrenches 19 are arranged in the termination region 10 b so as tosurround the first trenches 14 of the active region 10 a. As a result,even in the termination region 10 b, since the arrangement of the firsttrench 14 and the second trench 19 is equivalent to that of the adjacentfirst trenches 14 in the active region 10 a, it is possible to make thebreakdown voltage in the termination region 10 b equal to the breakdownvoltage in the active region 10 a. Therefore, it is possible to obtain asemiconductor device capable of improving the breakdown voltage of thetermination region.

Here, the case where the first conductivity type is n type and thesecond conductivity type is p type has been described, but the firstconductivity type may be p type and the second conductivity type may ben type.

The case where the semiconductor substrate 22 is a silicon substrate hasbeen described, but the substrate is not particularly limited. Othersemiconductor substrates such as SiC substrates, GaN substrates, and thelike may also be used.

Embodiment 2

The semiconductor device according to another embodiment will bedescribed with reference to FIGS. 7A to 7C.

FIGS. 7A to 7C shows an impurity concentration distribution of asemiconductor device and an electric field distribution of an activeregion, FIG. 7A shows a cross-sectional view of a main part of thesemiconductor device as in FIG. 1B, FIG. 7B is an impurity concentrationdistribution diagram, and FIG. 7C is an electric field distributiondiagram.

In the present embodiment, the same reference numerals are given to thesame constituent parts as those of the above-described Embodiment 1, anddescription of the same parts will be omitted, and different parts willbe described. The present embodiment is different from Embodiment 1 inthat the third impurity concentration n3 is lower than the firstimpurity concentration n1.

That is, as shown in FIG. 7B, in the semiconductor device of the presentembodiment, the semiconductor layer 11 has three levels of impurityconcentration distribution represented by n3<n1<n2. The second impurityconcentration n2 may be, for example, 5×10¹⁵ cm⁻³ to 1×10¹⁷ cm⁻³. Thefirst impurity concentration n1 may be 1×10¹⁵ cm⁻³ to 1×10¹⁷ cm⁻³. Thethird impurity concentration n3 may be set to 1×10¹⁵ cm⁻³ to 1×10¹⁷cm⁻³, in a range lower than the first impurity concentration n1.

As shown in FIG. 7C, since the third impurity concentration n3 is lowerthan the first impurity concentration n1, the slope of the electricfield peak at the end of the gate electrode 16 is reduced, and thereforethe decrease of the electric field at the second portion 11 d isprevented. It is possible to further improve the breakdown voltage ofthe active region 10 a. The breakdown voltage in the termination region10 b is basically equal to the breakdown voltage of the active region 10a.

As described above, the semiconductor layer 11 of the present embodimenthas three levels of impurity concentration distribution represented byn3<n1<n2. As a result, the slope of the electric field peak at the endof the gate electrode 16 becomes small, and the decrease of the electricfield at the second portion 11 d is prevented. It is possible to furtherimprove the breakdown voltage in the active region 10 a and thetermination region 10 b. Therefore, it is possible to obtain asemiconductor device capable of improving the breakdown voltage of thetermination region.

Here, the case where the first impurity concentration n1 is lower thanthe second impurity concentration n2 in the impurity concentrationdistribution in which the third impurity concentration n3 is lower thanthe first impurity concentration n1 has been described, but an impurityconcentration distribution in which the first impurity concentration n1and the second impurity concentration n2 are equal to each other may beused.

FIG. 8 is a diagram showing an impurity concentration distribution inwhich the first impurity concentration n1 and the second impurityconcentration n2 are substantially equal and the third impurityconcentration n3 is lower than the first impurity concentration n1(n3<n2=n1).

As shown in FIG. 8, the first impurity concentration n1 is set to 5×10¹⁵cm⁻³ to 1×10¹⁷ cm⁻³ which is the same as the second impurityconcentration n2, and the third impurity concentration n3 is set to1×10¹⁵ cm⁻³ to 1×10¹⁷ cm⁻³, in a range lower than the first impurityconcentration n1. The impurity concentration shown in FIGS. 7A to 7C areso-called three-level impurity concentration distributions, whereas theimpurity concentration distribution shown in FIG. 8 is a so-calledtwo-level impurity concentration distribution.

Even with the two-level impurity concentration distribution shown inFIG. 8, it is possible to obtain the effect of the impurityconcentration distribution shown in FIG. 2B and the effect of theimpurity concentration distribution shown in FIG. 7B. That is, since theelectric field distribution becomes flat, improvement of the breakdownvoltage is expected. Specifically, as described above, the impurityconcentration of the second portion 11 d is higher than that of thesemiconductor layer of the comparative example. As a result, the drainvoltage increases and a punch-through state occurs when a depletionlayer reaches the second portion 11 d having a high impurityconcentration, whereby the electric field is increased as compared withthe semiconductor layer of the comparative example. As a result, thebreakdown voltage in the active region 10 a is improved and theon-resistance is reduced.

Since the third impurity concentration n3 is lower than the firstimpurity concentration n1, the slope of the electric field peak at theend of the gate electrode 16 is reduced, and therefore the decrease ofthe electric field at the second portion 11 d is prevented. It ispossible to further improve the breakdown voltage of the active region10 a.

In addition, in the step shown in FIG. 5A, when epitaxially growing thefirst portion 11 c and the second portion 11 d, since the two-levelimpurity concentration distribution may be maintained constant withoutchanging a doping gas flow rate, there is also an advantage that theprocess may be simplified.

Embodiment 3

The semiconductor device according to the present embodiment will bedescribed with reference to FIGS. 9A to 10C.

FIGS. 9A to 9C show an impurity concentration distribution of asemiconductor device and an electric field distribution of an activeregion, FIG. 9A shows a cross-sectional view of a main part of thesemiconductor device as in FIG. 1B, FIG. 9B is an impurity concentrationdistribution diagram, and FIG. 9C is an electric field distributiondiagram.

FIGS. 10A to 10C are diagrams showing an electric field distribution ofa termination region of the semiconductor device, FIG. 10A is anenlarged plan view near the boundary between the active region and thetermination region, FIG. 10B is a cross-sectional view taken along lineD-D of FIG. 10A and viewed in the direction of the arrow, and FIG. 10Cis an electric field distribution diagram.

In this embodiment, the same reference numerals are given to the sameconstituent parts as those of the above-described Embodiment 1,description of the parts will be omitted, and different parts will bedescribed. This embodiment is different from Embodiment 1 in that theimpurity concentration of the semiconductor layer continually changes inthe depth direction of the semiconductor layer.

That is, as shown in FIG. 9B, in the semiconductor device of the presentembodiment, the semiconductor layer 11 has a so-called slope-shapedimpurity concentration distribution in which the impurity concentrationgradually decreases in a direction from the second surface 11 b side tothe first surface 11 a side. In one example, the impurity concentrationdistribution linearly decreases from an initial value set at 1×10¹⁷cm⁻³.

As shown in FIG. 9C, the electric field distribution has a steeper slopein the vicinity of the bottom portion of the first trench 14 than in thecomparative example. This is because the impurity concentration in thevicinity of the bottom portion of the first trench 14 is higher than theimpurity concentration in the comparative example, and therefore thedepletion layer hardly elongates.

The breakdown voltage in the active region 10 a is basically equal tothe breakdown voltage in the active region 10 a of Embodiment 1.

As shown in FIGS. 10A to 10C, by providing the second trench 19surrounding the first trenches 14, the structure in the longitudinaldirection (X direction) of the first trench 14 in the termination region10 b is equivalent to that in the active region 10 a. The impurityconcentration in the longitudinal direction of the first trench 14 isconstant, but by adding the second trench 19, the electric fielddistribution becomes equal to that of the active region 10 a. It ispossible to improve the breakdown voltage of the termination region 10b.

As described above, in the semiconductor device of the presentembodiment, the semiconductor layer 11 has a slope-shaped impurityconcentration distribution gradually decreasing in a direction from thesecond surface 11 b side to the first surface 11 a side. Also with theslope-shaped impurity concentration distribution, the breakdown voltageof the active region 10 a and the termination region 10 b is the same asthat of Embodiment 1, and the breakdown voltage of the terminationregion 10 b may be improved. Therefore, it is possible to obtain asemiconductor device capable of improving the breakdown voltage of thetermination region.

Here, the case where the continually changing impurity concentrationdistribution is slope-like is described, but it is also possible to makethe inclined impurity concentration distribution stepwise. FIG. 11 is adiagram showing the stepwise declining impurity concentrationdistribution.

As shown in FIG. 11, when the impurity concentration distribution of thesemiconductor layer 11 is stepwise, the second impurity concentration n2of the second portion 11 d is lower than the first impurityconcentration n1 of the first portion 11 c and the third impurityconcentration n3 of the third portion 11 e is lower than the secondimpurity concentration n2 (n3<n2<n1). The first impurity concentrationn1 may be set to 1×10¹⁷ cm⁻³, which is the same as the initial value ofthe slope-like impurity concentration distribution. Even when thedeclining impurity concentration distribution is stepwise, it ispossible to improve the breakdown voltage of the terminal region 10 b asin the case of the slope-shaped impurity concentration distribution.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor layer having a first surface and a second surface oppositeto the first surface, the semiconductor layer including: a gradientimpurity concentration region of a first conductivity type; a firstsemiconductor region of a second conductivity type located between thegradient impurity concentration region and the first surface; a secondsemiconductor region of the first conductivity type located between thefirst semiconductor region and the first surface; one or more firsttrenches extending from the first surface into the gradient impurityconcentration region; and a second trench extending from the firstsurface into the gradient impurity concentration region and surroundingthe first trench; a first electrode provided in the first trench andsurrounded by a first insulating film in the first trench; a secondelectrode provided in the first trench and surrounded by a secondinsulating film in the first trench; a third electrode provided in thesecond trench and surrounded by a third insulating film in the secondtrench, wherein the gradient impurity concentration region continuouslyincludes a first subregion at a first depth range from the firstsurface, a second subregion at a second depth range from the firstsurface that is shallower than the first depth range, and a thirdsubregion at a third depth range from the first surface that isshallower than the second depth range, and the first subregion has afirst impurity concentration, the second subregion has a second impurityconcentration, and the third subregion has a third impurityconcentration lower than the second impurity concentration.
 2. Thesemiconductor device according to claim 1, wherein the second impurityconcentration is higher than the first impurity concentration.
 3. Thesemiconductor device according to claim 2, wherein the first impurityconcentration and the third impurity concentration are substantiallyequal.
 4. The semiconductor device according to claim 2, wherein thethird impurity concentration is lower than the first impurityconcentration.
 5. The semiconductor device according to claim 1, whereinthe second impurity concentration is substantially equal to the firstimpurity concentration.
 6. The semiconductor device according to claim1, wherein the second impurity concentration is lower than the firstimpurity concentration.
 7. The semiconductor device according to claim1, wherein the semiconductor device includes an active region and atermination region, and the first trench is provided in the activeregion, and the second trench is provided in the termination region ofthe semiconductor device.
 8. The semiconductor device according to claim1, wherein a plurality of the first trenches extend in a first planedirection and are spaced from one another at a predetermined interval ina second plane direction crossing the first plane direction, a firstpart of the second trench extends in the first plane direction along aclosest one of the first trenches, and a distance between the closestone of the first trenches and the first part of the second trench in thesecond plane direction is substantially equal to the predeterminedinterval.
 9. The semiconductor device according to claim 8, wherein asecond part of the second trench extends in the second plane direction,and a distance between at least one of the first trenches and the secondpart of the second trench is equal to the predetermined interval.
 10. Asemiconductor device, comprising: a semiconductor layer, thesemiconductor layer including: a gradient impurity concentration regionof a first conductivity type; a first semiconductor region of a secondconductivity type located between the gradient impurity concentrationregion and the first surface; a second semiconductor region of the firstconductivity type located between the first semiconductor region and thefirst surface; one or more first trenches extending from the firstsurface into the gradient impurity concentration region; and a secondtrench extending from the first surface into the gradient impurityconcentration region and surrounding the first trench; a first electrodeprovided in the first trench and surrounded by a first insulating filmin the first trench; a second electrode provided in the first trench andsurrounded by a second insulating film in the first trench; and a thirdelectrode provided in the second trench and surrounded by a thirdinsulating film in the second trench, wherein an impurity concentrationin the gradient impurity concentration region gradually decreases in adepth direction from the first surface toward the second surface. 11.The semiconductor device according to claim 10, wherein the impurityconcentration in the gradient impurity concentration region continuouslydecreases in the depth direction.
 12. The semiconductor device accordingto claim 10, wherein the semiconductor device includes an active regionand a termination region, and the first trench is provided in the activeregion, and the second trench is provided in the termination region ofthe semiconductor device.
 13. The semiconductor device according toclaim 10, wherein a plurality of the first trenches are provided, theplurality of the first trenches extending in a first plane direction andbeing spaced from one another at a predetermined interval in a secondplane direction crossing the first plane direction, a first part of thesecond trench extends in the first plane direction along a closest oneof the first trenches, and a distance between the closest one of thefirst trenches and the first part of the second trench in the secondplane direction is substantially equal to the predetermined interval.14. The semiconductor device according to claim 13, wherein a secondpart of the second trench extends in the second plane direction, and adistance between at least one of the first trenches and the second partof the second trench is equal to the predetermined interval.